Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (Lecture Notes in Electrical Engineering, 184)

Ogras, Umit Y. Y.; Marculescu, Radu

ISBN 10: 9400798652 / ISBN 13: 9789400798656

Verlag: Springer, 2015

Beschreibung

Bestandsnummer des Verkäufers I-9789400798656

Bibliografische Details

• Titel: Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (Lecture Notes in Electrical Engineering, 184)
• Verlag: Springer
• Erscheinungsjahr: 2015
• Sprache: Englisch
• ISBN-10: 9400798652
• ISBN-13: 9789400798656
• Einband: Softcover
• Zustand: New

Über diesen Titel

Inhaltsangabe

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

Von der hinteren Coverseite

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.