A Novel approach for Fault Tolerant Nano Memory Applications. Dieser Artikel ist nicht verfügbar.A Novel approach for Fault Tolerant Nano Memory Applications

NANOTECHNOLOGY provides smaller, faster, and lower energy devices which allow more powerful and compact circuitry; However, these benefits come with a cost—the nanoscale devices may be less reliable. Thermal- and shot-noise estimations alone suggest that the transient fault rate of an individual nanoscale device (e.g., transistor or nanowire) may be orders of magnitude higher than today’s devices. A failure is said to have occurred in a circuit or system if it deviates from its specified behavior. A fault on the other hand is physical defect which may or may not cause a failure. The failure rate, also known as the hazard rate and defined as number of failures per unit time compared with the number of surviving components. A fault is characterized by its nature, value, extent & duration.

Ch Pavan Kumar received B.Tech in ECE & M.Tech in VLSI from Jawaharlal Nehru Technological University Hyderabad, India, Currently; he is pursing the Ph.D. degree in JNTUH, Hyd. Presently working as Assistant Professor, Dept. of ECE, KITS, Warangal. His research includes VLSI design, Ultra Low Power Designs and Sub threshold region modelling.