OPTIMAL DG PLACEMENT FOR VOLTAGE IMPROVEMENT USING PSO: Loss Reduction and THD Reduction. Dieser Artikel ist nicht verfügbar.OPTIMAL DG PLACEMENT FOR VOLTAGE IMPROVEMENT USING PSO: Loss Reduction and THD Reduction

The size and location of DG are the crucial factors in the application of DG for loss minimization. This book presents an algorithm for the identification of bus location using Sensitivity analysis and also an algorithm for the determination of size of the DG using PSO. This methodology is tested on IEEE 15 bus system. By installing DGs at all the potential locations with the determined sizes, the total real power loss of the system has been reduced by 83% and the voltage profile of the system is also improved. The harmonics that are present in the system are reduced by placing capacitors at the optimal locations which are determined by using PSO-HPF algorithm. By placing the capacitors at optimal locations, the voltage profile is also improved.

BESTA HARIPRASAD, received his B.Tech degree in Electrical and Electronics Engineering in the year of 2010 and M.Tech degree in Electrical Power Engineering in the year of 2013. Curently, he is a Ph.D Scholar in Jawaharlal Nehru Technical University Anantapur.Dr. G SREENIVASAN, Professor, Department of EEE, P.V.K.K.I.T.