Power-Constrained Testing of VLSI Circuits (Hardcover)

Nicola Nicolici

ISBN 10: 140207235X / ISBN 13: 9781402072352

Verlag: Kluwer Academic Publishers, New York, NY, 2003

Beschreibung

Hardcover. Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented. Focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. This text surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

Bestandsnummer des Verkäufers 9781402072352

Bibliografische Details

• Titel: Power-Constrained Testing of VLSI Circuits (Hardcover)
• Verlag: Kluwer Academic Publishers, New York, NY
• Erscheinungsjahr: 2003
• Sprache: Englisch
• ISBN-10: 140207235X
• ISBN-13: 9781402072352
• Einband: Hardcover
• Zustand: new

Über diesen Titel

Inhaltsangabe

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.