Power Efficient Security for IOT Devices

Khaled Tarek

ISBN 10: 6139826098 / ISBN 13: 9786139826094

Verlag: LAP LAMBERT Academic Publishing, 2019

Beschreibung

nach der Bestellung gedruckt Neuware - Printed after ordering - The Internet of Things is a novel paradigm that is rapidly gaining ground in the scenario of modern wireless telecommunications. However, security of IoT systems is considered as one of the most important challenges facing system developers. The proposed design is a power adaptive encryption solution that provides four different encryption configurations which are AES-256, AES-192, AES-128, and DES. The IoT device can switch between the four configurations depending on the available power budget for encryption. The design uses Partial Dynamic Reconfiguration (PDR) technology to allow the switching between the four configurations using minimal area and power consumption. The proposed design was tested on a ZedBoard development board after being synthesized using Xilinx Vivado.

Bestandsnummer des Verkäufers 9786139826094

Bibliografische Details

• Titel: Power Efficient Security for IOT Devices
• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsjahr: 2019
• Sprache: Englisch
• ISBN-10: 6139826098
• ISBN-13: 9786139826094
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 220B x 150 H x 10 T Millimeter Breite: 220 mm, Höhe: 150 mm, Tiefe: 10 mm
• Gewicht: 244 Gramm

Über diesen Titel

Inhaltsangabe

The Internet of Things is a novel paradigm that is rapidly gaining ground in the scenario of modern wireless telecommunications. However, security of IoT systems is considered as one of the most important challenges facing system developers. The proposed design is a power adaptive encryption solution that provides four different encryption configurations which are AES-256, AES-192, AES-128, and DES. The IoT device can switch between the four configurations depending on the available power budget for encryption. The design uses Partial Dynamic Reconfiguration (PDR) technology to allow the switching between the four configurations using minimal area and power consumption. The proposed design was tested on a ZedBoard development board after being synthesized using Xilinx Vivado.