LOW power design is playing an important role in today ultra-large scale integration (ULSI) design, particularly as we continue to double the number of transistors on a die every two years and increase the frequency of operation at fairly the same rate. Certainly, an important aspect of low power faces with mobile communications and it has a huge impact on our lives, as we are at the start-line of the proliferation of mobile PDA’s (Personal Digital Assistants), Wireless LAN and portable multi-media computing. All of these devices are shaping the way we will be interacting with our family, peers and workplace, thus requiring also a new and innovative low power design paradigm. Furthermore, low power design techniques are becoming paramount in high performance desktop, base-station and server applications, such as high-speed microprocessors, where excess in power dissipation can lead to a number of cooling, reliability and signal integrity concerns severely burdening the total industrialcost. Hence, low power design can be easily anticipated to further come into prominence as we move to next generation System-on-Chip and Network-on-Chip designs. This book is entirely devoted to disseminate the results of a long term research program between Politecnico di Milano (Italy) and STMic- electronics, in the field of architectural exploration and optimization techniques to designing low power embedded systems.

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This volume introduces innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance VLIW microprocessors. A VLIW processor is a (generally) pipelined processor that can execute, in each clock cycle, a set of explicitly parallel operations.

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