RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Stuart Sutherland

ISBN 10: 1546776346 / ISBN 13: 9781546776345

Verlag: Createspace Independent Publishing Platform, 2017

Beschreibung

This item is printed on demand. New copy - Usually dispatched within 5-9 working days 703. Bestandsnummer des Verkäufers C9781546776345

Bibliografische Details

Titel: RTL Modeling with SystemVerilog for ...

Verlag: Createspace Independent Publishing Platform

Erscheinungsdatum: 2017

Einband: Paperback / softback

Zustand: New

Über diesen Titel

Reseña del editor:

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”