Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.

�ber die Autorin bzw. den Autor

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.

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