Robust SRAM Designs and Analysis

Jawar Singh

ISBN 10: 1461408172 / ISBN 13: 9781461408178

Verlag: Springer New York, Springer US Jul 2012, 2012

Beschreibung

Neuware -This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis;Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 180 pp. Englisch.

Bestandsnummer des Verkäufers 9781461408178

Bibliografische Details

• Titel: Robust SRAM Designs and Analysis
• Verlag: Springer New York, Springer US Jul 2012
• Erscheinungsjahr: 2012
• Sprache: Englisch
• ISBN-10: 1461408172
• ISBN-13: 9781461408178
• Einband: Buch
• Zustand: Neu
• Abmessungen: 241B x 160 H x 15 T Millimeter Breite: 241 mm, Höhe: 160 mm, Tiefe: 15 mm
• Gewicht: 442 Gramm

Über diesen Titel

Inhaltsangabe

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.

• Provides a complete and concise introduction to SRAM bitcell design and analysis;
• Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
• Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
• Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.