Routing Congestion in VLSI Circuits

Saxena, Prashant; Shelar, Rupesh S. (Intel Corporation); Sapatnekar, Sachin S.

ISBN 10: 1441940138 / ISBN 13: 9781441940131

Verlag: Springer-Verlag New York Inc., 2010

Beschreibung

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. Series: Integrated Circuits and Systems. Num Pages: 250 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 14. Weight in Grams: 409. . 2010. 1st ed. Softcover of orig. ed. 2007. Paperback. . . . . Books ship from the US and Ireland.

Bestandsnummer des Verkäufers V9781441940131

Bibliografische Details

• Titel: Routing Congestion in VLSI Circuits
• Verlag: Springer-Verlag New York Inc.
• Erscheinungsjahr: 2010
• Sprache: Englisch
• ISBN-10: 1441940138
• ISBN-13: 9781441940131
• Einband: Softcover
• Zustand: New

Über diesen Titel

Inhaltsangabe

This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Von der hinteren Coverseite

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.

Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.

Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.