Statistical Analysis and Optimization for Vlsi: Timing and Power

Ashish Srivastava

ISBN 10: 1441938273 / ISBN 13: 9781441938275

Verlag: SPRINGER NATURE Dez 2010, 2010

Beschreibung

This item is printed on demand - it takes 3-4 days longer - Neuware -Covers the statistical analysis and optimization issues arising due to increased process variations in current technologies. Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research. Written byauthor who lead much research in this area who provide novel ideas and approaches to handle the addressed issues 280 pp. Englisch.

Bestandsnummer des Verkäufers 9781441938275

Bibliografische Details

• Titel: Statistical Analysis and Optimization for Vlsi: Timing and Power
• Verlag: SPRINGER NATURE Dez 2010
• Erscheinungsjahr: 2010
• Sprache: Englisch
• ISBN-10: 1441938273
• ISBN-13: 9781441938275
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 234B x 156 H x 15 T Millimeter Breite: 234 mm, Höhe: 156 mm, Tiefe: 15 mm
• Gewicht: 413 Gramm

Über diesen Titel

Inhaltsangabe

Covers the statistical analysis and optimization issues arising due to increased process variations in current technologies. It focuses on timing and power analysis techniques, developed during the past couple of years, which will lead to parametric yield analysis techniques. Optimization approaches suitable in non-deterministic scenarios which improve the yield of the design are also explained. This book comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research. The authors have been leading a lot of the research in this area and will also provide novel ideas and approaches to handle the addressed issues.

Über die Autorin bzw. den Autor

Ashish Srivastava received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur in 2001 and the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor in 2003. He is currently pursuing the Ph.D. degree at the University of Michigan, Ann Arbor. In summe r 2003 he was with the Technology CAD Division, Intel Corporation, Hillsboro, where he was a Graduate Intern and in summer 2004 he was with the Austin Research Lab, IBM, where he worked on leakage power optimization techniques . He is a recipient of the Intel PhD Fellowship, 2004. His research interests include optimization and statistical techniques for low-power VLSI design. Dennis Sylvester received the B.S. degree in electrical engineering summa cum laude from the University of Michigan, Ann Arbor, in 1995. He received the M.S. and Ph.D. degrees in electrical engineering from University of California, Berkeley, in 1997 and 1999, respectively. He worked at Hewlett-Packard Laboratories in Palo Alto, CA, from 1996 to 1998. His dissertation research was recognized with the 2000 David J. Sakrison Memorial Prize as the most outstanding research in the UC-Berkeley EECS department. After working as a Senior R&D Engineer in the Advanced Technology Group of Synopsys, Mountain View, CA, he is now an Assistant Professor of Electrical Engineering at the University of Michigan, Ann Arbor. He has published numerous articles in his field of research, which includes the modeling, characterization, and analysis of on-chip interconnect, low-power circuit design and design automation techniques, and variability-aware circuit approaches. Dr. Sylvester received an NSF CAREER award, the 2000 Beatrice Winner Award at ISSCC, two outstanding research presentation awards from the Semiconductor Research Corporation, and a best student paper award at the 1997 International Semiconductor Device Research Symposium. He is the recipient of the 2003 ACM SIGDA Outstanding New Faculty Award and the 1938E Award for teaching and mentoring, which is the highest award given to a junior faculty in the Michigan College of Engineering. He has served on the technical program committee of numerous design automation and circuit design conferences and was general chair for the 2003 ACM/IEEE System-Level Interconnect Prediction (SLIP) Workshop. In addition, he helps to define the circuit and physical design roadmap as a member of the International Technology Roadmap for Semiconductors (ITRS) U.S. Design Technology Working Group. He is a member of IEEE, ACM, American Society of Engineering Education, and Eta Kappa Nu. David Blaauw received his B.S. in Physics and Computer Science from Duke University in 1986, his M.S. in Computer Science from the University of Illinois, Urbana, in 1988 and his Ph.D. in Computer Science from the University of Illinois, Urbana, in 1991. He worked at the Engineering Accelerator Technology Division, IBM Corporation, Endicott, as a Development Staff Member, until August 1993. From 1993 till August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of t he High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan as an Associate Professor. His work has focused on VLSI design and CAD with particular emphasis on circuit analysis and optimization problems for high performance and low power designs. He was the Technical Program Chair and General Chair for the International Symposium on Low Power Electronic and Design in 1999 and 2000, respectively, and was the Technical Program Co-Chair and member of the Executive Committee the ACM/IEEE Design Automation Conference in 2000 and 2001.