SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Spear, Chris

ISBN 10: 0387765298 / ISBN 13: 9780387765297

Verlag: Springer, 2008

Beschreibung

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Bestandsnummer des Verkäufers S_362037104

Bibliografische Details

• Titel: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
• Verlag: Springer
• Erscheinungsjahr: 2008
• Sprache: Englisch
• ISBN-10: 0387765298
• ISBN-13: 9780387765297
• Einband: Hardcover
• Auflage: 2. Auflage
• Zustand: Good

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Inhaltsangabe

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

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New! Expanded! Updated!Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include:The revision of nearly every explanation and code sampleThe inclusion of new chapters: "A Complete SystemVerilog Testbench" with a complete constrained random testbench for an ATM switch and "Interfacing with C" on the DPI (Directed Programming Interface)The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter fourAn expanded index with 50% more entries and cross references"As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs."Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge"It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first!The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!"Stuart Sutherland, SystemVerilog Training Consultant, Sutherland HDL, Inc.Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog s verification constructs.Testbenches are growing more complex. You need this book to keep up.Includes nearly 500 code samples and 70 figures.