Timing Optimization Through Clock Skew Scheduling

Ivan S. Kourtev

ISBN 10: 0792377966 / ISBN 13: 9780792377962

Verlag: Springer US, Springer New York, 2000

Beschreibung

Druck auf Anfrage Neuware - Printed after ordering - History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops.

Bestandsnummer des Verkäufers 9780792377962

Bibliografische Details

• Titel: Timing Optimization Through Clock Skew Scheduling
• Verlag: Springer US, Springer New York
• Erscheinungsjahr: 2000
• Sprache: Englisch
• ISBN-10: 0792377966
• ISBN-13: 9780792377962
• Einband: Buch
• Zustand: Neu
• Abmessungen: 241B x 160 H x 17 T Millimeter Breite: 241 mm, Höhe: 160 mm, Tiefe: 17 mm
• Gewicht: 500 Gramm

Über diesen Titel

Inhaltsangabe

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur­ rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen­ tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta­ tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net­ work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de­ velopments in this area have been slow to reach the designers’ desktops.