The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

Ray Salemi

ISBN 10: 0974164933 / ISBN 13: 9780974164939

Verlag: Boston Light Press, 2013

Beschreibung

This item is printed on demand. New copy - Usually dispatched within 5-9 working days 498.

Bestandsnummer des Verkäufers C9780974164939

Bibliografische Details

• Titel: The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology
• Verlag: Boston Light Press
• Erscheinungsjahr: 2013
• Sprache: Englisch
• ISBN-10: 0974164933
• ISBN-13: 9780974164939
• Einband: Paperback / softback
• Zustand: New

Über diesen Titel

Inhaltsangabe

The UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM knowledge before a job interview to be able to confidently answer questions such as "What is a uvm_agent?" , "How do you use uvm_sequences?", and "When do you use the UVM's factory." The UVM Primer's downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on www.uvmprimer.com) to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM.

Über die Autorin bzw. den Autor

Ray Salemi is a senior verification consultant with Mentor Graphics. Salemi started his career in Electronic Design Automation with Gateway Design Automation, the inventors of Verilog. Since then he has worked for Cadence Design Systems, Sun Microsystems, and several startups. Ray Salemi is the author of the popular introduction to simulation, FPGA SIMULATION.