Titel: Universal Verification Methodology Based Verification Environment (Paperback or Softback)
Verlag: LAP Lambert Academic Publishing 1/19/2014
Erscheinungsjahr: 2014
Sprache: Englisch
ISBN-10: 3659476048
ISBN-13: 9783659476044
Einband: Paperback or Softback
Zustand: New
Buchtyp: Book

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Inhaltsangabe

Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.

�ber die Autorin bzw. den Autor

Abhishek Jain, Technical Manager at STMicroelectronics, India, has done M.Tech in Computer Science from IETE, M.Sc. Electronics from University of Delhi and PGDBA in Operations Management from Symbiosis. Driving key activities on Functional Verification Flow in Imaging group of STMicroelectronics.Doing Research in Efficient Verification Management.

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