VLSI Fault Modeling and Testing Techniques (Hardcover)

George W. Zobrist

ISBN 10: 0893917818 / ISBN 13: 9780893917814

Verlag: Bloomsbury Publishing Plc, Westport, 1993

Beschreibung

Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Bestandsnummer des Verkäufers 9780893917814

Bibliografische Details

• Titel: VLSI Fault Modeling and Testing Techniques (Hardcover)
• Verlag: Bloomsbury Publishing Plc, Westport
• Erscheinungsjahr: 1993
• Sprache: Englisch
• ISBN-10: 0893917818
• ISBN-13: 9780893917814
• Einband: Hardcover
• Zustand: new

Über diesen Titel

Inhaltsangabe

VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

Über die Autorin bzw. den Autor

brist /f George /i W.