VLSI Implementation of MIMO Signal Processing Algorithms

Mahdi Shabany

ISBN 10: 3848497638 / ISBN 13: 9783848497638

Verlag: LAP LAMBERT Academic Publishing Apr 2012, 2012

Beschreibung

This item is printed on demand - it takes 3-4 days longer - Neuware -The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for MIMO systems with large number of antennas in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this book introduces a novel scalable pipelined VLSI ar- chitecture for a 4 X 4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of dis- tributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The pro- posed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput than currently reported schemes. 208 pp. Englisch.

Bestandsnummer des Verkäufers 9783848497638

Bibliografische Details

• Titel: VLSI Implementation of MIMO Signal Processing Algorithms
• Verlag: LAP LAMBERT Academic Publishing Apr 2012
• Veröffentlichungsdatum: 2012
• Sprache: Englisch
• ISBN-10: 3848497638
• ISBN-13: 9783848497638
• Bindung: Taschenbuch
• Zustand: Neu

Über diesen Titel

Inhaltsangabe

The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for MIMO systems with large number of antennas in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this book introduces a novel scalable pipelined VLSI ar- chitecture for a 4 X 4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of dis- tributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The pro- posed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput than currently reported schemes.