Vedic Mathematics for Binary Applications

Abhijeet Kumar

ISBN 10: 3659543306 / ISBN 13: 9783659543302

Verlag: LAP LAMBERT Academic Publishing Okt 2018, 2018

Beschreibung

Neuware -Conventional 24x24 multiply architectures are implemented in floating point multipliers using array multipliers, redundant binary architectures( Pipeline Stages), modified booth encoding, a binary tree of 4:2 Compressors (Wallace tree) and modified carry save array in conjunction with Booth's algorithm. There are number of problems associated with tree and array multipliers. Tree multipliers have many problems like shortest logic delay but irregular layouts with complicated interconnects, irregular layouts not only demand more physical design effort, but also introduce significant interconnect delay. Similarly, array multipliers has also some drawbacks associated with them such as they have larger delay and offer regular layout with simpler interconnects. Also significant amount of power consumption as reconfigurability at run time is not provided according to the input bit width. In order to remove the above problems, Urdhvatriyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized. Simulation of 32-bit Floating Point Multiplier and application of Vedic Mathematics is an important part of this dissertation.Books on Demand GmbH, Überseering 33, 22297 Hamburg 52 pp. Englisch.

Bestandsnummer des Verkäufers 9783659543302

Bibliografische Details

• Titel: Vedic Mathematics for Binary Applications
• Verlag: LAP LAMBERT Academic Publishing Okt 2018
• Erscheinungsjahr: 2018
• Sprache: Englisch
• ISBN-10: 3659543306
• ISBN-13: 9783659543302
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 220B x 150 H x 4 T Millimeter Breite: 220 mm, Höhe: 150 mm, Tiefe: 4 mm
• Gewicht: 96 Gramm

Über diesen Titel

Inhaltsangabe

Conventional 24x24 multiply architectures are implemented in floating point multipliers using array multipliers, redundant binary architectures( Pipeline Stages), modified booth encoding, a binary tree of 4:2 Compressors (Wallace tree) and modified carry save array in conjunction with Booth's algorithm. There are number of problems associated with tree and array multipliers. Tree multipliers have many problems like shortest logic delay but irregular layouts with complicated interconnects, irregular layouts not only demand more physical design effort, but also introduce significant interconnect delay. Similarly, array multipliers has also some drawbacks associated with them such as they have larger delay and offer regular layout with simpler interconnects. Also significant amount of power consumption as reconfigurability at run time is not provided according to the input bit width. In order to remove the above problems, Urdhvatriyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized. Simulation of 32-bit Floating Point Multiplier and application of Vedic Mathematics is an important part of this dissertation.