Verilog Styles for Synthesis of Digital Systems

Smith, David R., Franzon, Paul D.

ISBN 10: 0201618605 ISBN 13: 9780201618600
Verlag: Pearson Education, Limited, 2000
Gebraucht Softcover

Verkäufer Better World Books, Mishawaka, IN, USA Verkäuferbewertung 5 von 5 Sternen 5 Sterne, Erfahren Sie mehr über Verkäufer-Bewertungen

AbeBooks-Verkäufer seit 3. August 2006


Beschreibung

Beschreibung:

Pages intact with minimal writing/highlighting. The binding may be loose and creased. Dust jackets/supplements are not included. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good. Bestandsnummer des Verkäufers 6234725-75

Diesen Artikel melden

Inhaltsangabe:

For senior/graduate-level courses in Digital Hardware Design/Verilog.

This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students―e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.

Von der hinteren Coverseite:

The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester.

Features:

  • The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader.
  • It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation.
  • Large number of examples; from 100-100k gate equivalents.
  • Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.

„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.

Bibliografische Details

Titel: Verilog Styles for Synthesis of Digital ...
Verlag: Pearson Education, Limited
Erscheinungsdatum: 2000
Einband: Softcover
Zustand: Good

Beste Suchergebnisse bei AbeBooks

Es gibt 1 weitere Exemplare dieses Buches

Alle Suchergebnisse ansehen