brayton robert (163 Ergebnisse)

Hardcover. Zustand: Good. No Jacket. Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 1.15.

Hardcover. Zustand: Sehr gut. 1st ed. 258 S. Very Good. Shrink wrapped. Sprache: Englisch Gewicht in Gramm: 710.

Zustand: Sehr gut. Zustand: Sehr gut | Seiten: 260 | Sprache: Englisch | Produktart: Bücher.

Zustand: Gut. Zustand: Gut | Seiten: 140 | Sprache: Englisch | Produktart: Sonstiges.

Zustand: Sehr gut. Zustand: Sehr gut | Seiten: 404 | Sprache: Englisch | Produktart: Bücher.

Zustand: Good. Some minor shelf wear otherwise in a very good condition throughout. Light dusting. Inscriptions at the front of the book. Clean and readable.

Soft Cover. Zustand: As New. First Edition. Unread 54 pages. Very crisp copy, a little toned at ends. Size: 12mo - over 6¾" - 7¾" tall.

Pamphlet. Zustand: Very Good. Vol 28, pp. 23-43, Illus, Extracted from orig vol, thus begins with title page, trimmed & stapled pamphlet, else VG.

Softcover. Zustand: Very Good with no dust jacket. Stapled binding is sound. Pages bright and clean. Wrappers have light handling wear. Contents: Brayton, A tentative royal descent for Daneil Dobyns of Essex Co., Va. Hopewell, Essex County voters in 1769. Finley, The John Finleys of Augusta County, Virginia: correcting the record (continued). Ross and Morgan, Gates families of the colonial Virginia counties of Henrico and Chesterfield (concluded). Pippenger, Marriage and death notices from the Alexandria Herald, 1811-1825 (continued). Burgess, William Brown (1758-1843) of Culpeper and Rappahannock Cos., Va., and his children. Mosman, Nicholas Cain, colonial Virginia planter, probably born Nicholas Kern in Germany. Loeser, Frances (Housden) (Tucker) Nelson and some relatives: correction. Clay, Some miscellaneous land office correspondence. Reviews. 9.0" inches tall; 78 pages.

Softcover. Zustand: Very Good with no dust jacket. Sound binding. Clean, off-white pages. Wrappers have light handling wear. Address label on back of wrappers. ; Contents: Freilich, Research in Pennsylvania. de Berardinis, Call names, dits, frenchifications, noms de guerre, particles, patronymics, phonetics, surname compounds, and translations! Intercultural name changes in America, as illustrated by the offspring of Marie Catherine Horn. deBarardinis, "Madame X": Virginie Amélie "Mimi" Avegno (Mme. Gautreau) and a family note to art history. Brayton, Check the original! Two lessons learned the hard way: Hardy of South Carolina - a "discreet" omission to hide an indiscretion. Proffitt, Mallory-Blunt of Virginia - a miscopied name blocks a line. Reviews. In memoriam: Dr. Gary Bernard Mills. ; 10.0" tall; 76 pages.

Zustand: New.

Zustand: Gut. Zustand: Gut | Seiten: 300 | Sprache: Englisch | Produktart: Bücher.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability. In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.

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Taschenbuch. Zustand: Neu. Neuware -The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 208 pp. Englisch.

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