zhao qian lin ping deng (1 Ergebnisse)

paperback. Zustand: New. Ship out in 2 business day, And Fast shipping, Free Tracking number will be provided after the shipment.Paperback. Pub Date: November 2012 Pages: 325 Language: Chinese in Publisher: Tsinghua University Press 21 colleges and universities planning materials and electronic information: Verilog digital system design and FPGA applications written in Verilog digital system design. front-end design flow HDL coding guidelines from the Verilog HDL language. logic card to the test platform. based on the application of the current mainstream the Altera FPGACPLD device introduction. and on-chip programmable system line depth. The book is easy-to-digest. step-by-step. easy entry. but also deep into the field of integrated circuit design. The book can be used as electronic. computer and information professional senior undergraduate and postgraduate teaching materials can also be used as a technical reference books for FPGA development of integrated circuit design engineer. Contents: Chapter 1 Introduction 1.1 IC design technology development 1.2 Verilog. the the HDL and VHDL1.2.1 The Verilog HDL. VHDL Development History 1.2.2 Verilog HDL and VHDL compare 1.3 FPGACPLD Introduction to programmable logic devices 1.3.1 Development History 1.3 . .2 PALGAL1.3.3 CPLD1.3.4 FPGA1.3.5 difference between CPLD and FPGA 1.3.6 SOPC exercises 1 Chapter 2 Verilog HDL basis 2.1 Verilog HDL's basic unit - module 2.1.1 simple Verilog HDL program instance 2.1.2 Verilog HDL 2.3 Operators and Expressions 2.2.2 Constants and its representation 2.2.3 variable data types 2.3.1 Arithmetic operators 2.1.3 logic functions of the basic structure of the program description 2.2 Verilog HDL syntax 2.2.1 lexical provisions 2.3.2 2.3.5 Equality operators. operators 2.3.3 Abbreviated operator 2.3.4 relational operators 2.3.6 logical operators 2.3.7 shift operator 2.3.8 the concatenation operator 2.3.9 conditions Operators 2.3. 10 priority levels 2.4 procedure statement 2.5 2.4.1 initial statement 2.4.2 always statement statement 2.5.1 serial block begin-end2.5.2 parallel block the fork-join2.6 assignment statement 2.6.1 Continuous assignment 2.6.2 process assignment 2.7 a description of the conditions of the conditional statement 2.7.1 if-else statement the 2.7.2 case statement 2.7.3 Completeness 2.8 loop statement 2.8.1 forever statement 2.8.2 repeat statement 2.8.3 while statement 2.8.4 for statement 2.8.5 disable statement 2.9 task and function description statement 2.9.1 task the statement 2.9.2 function description to statement 2.9.3 task and function description of the different points of the statement 2.10 compiled Wizard 2.10.1 macro definition statement. define2.10.2 file contains statements. include2.10.3 conditions compile command ifdef. else. endif2.10.4 time scale command. timescale2.11 Verilog HDL design example 2.11.1 combinational logic circuit used modeling described in 2.11.2 sequential logic circuit 2.12 Summary Exercises Chapter 3 Verilog HDL 3.1 Verilog HDL modeling description 3.1.1 structured modeling way to describe . Chapter 5. Chapter 4 of the finite state machine design Verilog coding style Chapter 6 logic verification and test platform Chapter 7 logic synthesis and static timing analysis section Chapter 8 the Altera FPGACPLD device and programming configuration Chapter 9 digital circuit and system design examples Chapter 10 programmable-chip system Appendix A common EDA software user guide in Appendix B DE2 introduce ReferencesFour Satisfaction guaranteed,or money back.