9780792380795 - a unified approach for timing verification and delay fault testing von sivaraman, mukund; strojwas, andrzej j. (21 Ergebnisse)
- Hardcover
Anbieter: Bay State Book Company, North Smithfield, RI, USABay State Book Company
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Ausreichend
EUR 42,72
Versand gratisVersand innerhalb von USAAnzahl: 1 verfügbar
Zustand: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Sprache: Englisch
Verlag: Kluwer Academic Publishers, Dordrecht, Holland, 1997
- Hardcover
- Erstausgabe
Anbieter: PsychoBabel & Skoob Books, Didcot, Vereinigtes KönigreichPsychoBabel & Skoob Books
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Gut
EUR 32,23
EUR 14,62 VersandVersand von Vereinigtes Königreich nach USAAnzahl: 1 verfügbar
hardcover. Zustand: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
- Hardcover
Anbieter: Mispah books, Redhill, SURRE, Vereinigtes KönigreichMispah books
Verkäufer/-in kontaktierenVerkäufer/-in mit 4 SternenZustand: Gebraucht - Wie neu
EUR 56,63
EUR 29,25 VersandVersand von Vereinigtes Königreich nach USAAnzahl: 1 verfügbar
Hardcover. Zustand: Like New. Like NewLIKE NEW. book.
- Hardcover
Anbieter: Basi6 International, Irving, TX, USABasi6 International
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 98,38
Versand gratisVersand innerhalb von USAAnzahl: 10 verfügbar
Zustand: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Hardcover
Anbieter: GreatBookPrices, Columbia, MD, USAGreatBookPrices
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 113,58
EUR 2,28 VersandVersand innerhalb von USAAnzahl: Mehr als 20 verfügbar
Zustand: New.
- Hardcover
Anbieter: BennettBooksLtd, Los Angeles, CA, USABennettBooksLtd
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 109,75
EUR 6,01 VersandVersand innerhalb von USAAnzahl: 1 verfügbar
hardcover. Zustand: New. In shrink wrap. Looks like an interesting title.
- Hardcover
Anbieter: GreatBookPrices, Columbia, MD, USAGreatBookPrices
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Wie neu
EUR 122,82
EUR 2,28 VersandVersand innerhalb von USAAnzahl: Mehr als 20 verfügbar
Zustand: As New. Unread book in perfect condition.
- Hardcover
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes KönigreichRia Christie Collections
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 116,74
EUR 14,01 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New. In.
- Hardcover
Anbieter: GreatBookPricesUK, Woodford Green, Vereinigtes KönigreichGreatBookPricesUK
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 116,72
EUR 17,55 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New.
- Hardcover
Anbieter: Buchpark, Trebbin, DeutschlandBuchpark
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Gut
EUR 35,62
EUR 105,00 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Zustand: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fa…brication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
Anbieter: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandKennys Bookshop and Art Galleries Ltd.
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 132,60
EUR 9,50 VersandVersand von Irland nach USAAnzahl: 15 verfügbar
Zustand: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, bio…graphy. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
- Hardcover
Anbieter: GreatBookPricesUK, Woodford Green, Vereinigtes KönigreichGreatBookPricesUK
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Wie neu
EUR 129,55
EUR 17,55 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: As New. Unread book in perfect condition.
- Hardcover
Anbieter: Books Puddle, New York, NY, USABooks Puddle
Verkäufer/-in kontaktierenVerkäufer/-in mit 4 SternenZustand: Neu
EUR 143,74
EUR 3,45 VersandVersand innerhalb von USAAnzahl: 4 verfügbar
Zustand: New. pp. 176.
- Hardcover
Anbieter: Kennys Bookstore, Olney, MD, USAKennys Bookstore
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 165,74
EUR 9,08 VersandVersand innerhalb von USAAnzahl: 15 verfügbar
Zustand: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, bio…graphy. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
- Hardcover
Anbieter: AHA-BUCH GmbH, Einbeck, DeutschlandAHA-BUCH GmbH
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 112,77
EUR 62,18 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre…-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
- Print-on-Demand
Anbieter: moluna, Greven, Deutschlandmoluna
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 92,27
EUR 48,99 VersandVersand von Deutschland nach USAAnzahl: Mehr als 20 verfügbar
Gebunden. Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, bot…h before and after fabrication. Research in .
- Hardcover
- Print-on-Demand
Anbieter: Majestic Books, Hounslow, Vereinigtes KönigreichMajestic Books
Verkäufer/-in kontaktierenVerkäufer/-in mit 4 SternenZustand: Neu
EUR 148,27
EUR 7,60 VersandVersand von Vereinigtes Königreich nach USAAnzahl: 4 verfügbar
Zustand: New. Print on Demand pp. 176 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
- Hardcover
- Print-on-Demand
Anbieter: Biblios, frankfurt am main, HESSE, DeutschlandBiblios
Verkäufer/-in kontaktierenVerkäufer/-in mit 4 SternenZustand: Neu
EUR 151,90
EUR 9,95 VersandVersand von Deutschland nach USAAnzahl: 4 verfügbar
Zustand: New. PRINT ON DEMAND pp. 176.
- Hardcover
- Print-on-Demand
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, DeutschlandBuchWeltWeit Ludwig Meier e.K.
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 139,09
EUR 23,00 VersandVersand von Deutschland nach USAAnzahl: 2 verfügbar
Buch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication.…Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing. 176 pp. Englisch.
Weitere Bilder- Hardcover
- Print-on-Demand
Anbieter: preigu, Osnabrück, Deutschlandpreigu
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 95,70
EUR 70,00 VersandVersand von Deutschland nach USAAnzahl: 5 verfügbar
Buch. Zustand: Neu. A Unified Approach for Timing Verification and Delay Fault Testing | Mukund Sivaraman (u. a.) | Buch | xv | Englisch | 1997 | Springer | EAN 9780792380795 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu… Print on Demand.
- Hardcover
- Print-on-Demand
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschlandbuchversandmimpf2000
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 106,99
EUR 60,00 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Buch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Rese…arch in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts.A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation.A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers.A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model.A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits.The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 176 pp. Englisch.
