ISBN: 9783659920134 - effect of underlap on device performance of gan based dg-mosfet (7 Ergebnisse)

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Taschenbuch. Zustand: Neu. Effect of Underlap On Device Performance of GaN Based DG-MOSFET | Md. Rokib Hasan (u. a.) | Taschenbuch | 68 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659920134 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications. 68 pp. Englisch.…

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications. …

Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Hasan Md. RokibI am Md. Rokib Hasan. My home town is Mymensingh, Bangladesh. I have completed my B.Sc. in Electrical and Electronics Engineering from American International University- Bangladesh (AIUB).I was nominated as a General S.…

Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch. …