9783838364049 - bias-temperature-instabilities in mosfets with high-k dielectrics: electrical behavior, modeling and process impact under bias temperature stress in high-k metal gated mosfets von aoulaiche, marc; groeseneken, guido; maes, herman (5 Ergebnisse)
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Taschenbuch. Zustand: Neu. Bias-Temperature-Instabilities in MOSFETs with high-k dielectrics | Electrical behavior, modeling and process impact under Bias Temperature stress in high-k metal gated MOSFETs | Marc Aoulaiche (u. a.) | Taschenbuch | 224 S. | Englisch | 2010 | LAP LAMBERT Academic Publishing | EAN 9783838364049 | Vera…ntwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -New MOSFET architectures are presently being developed in which dielectrics with high permittivity are introduced to replace SiO2-based dielectrics, which are at the end of the scaling roadmap, and where also metal gates are used to r…eplace poly-Si gate to avoid poly-depletion effects. Key in the success of this development is the electrical behavior of such high k/metal gate devices, and more specifically the Bias-Temperature- Instabilities, which are well-known reliability problems in MOS gate stacks. In this thesis, these Bias-Temperature effects will be investigated: the electrical behavior of the devices under Bias- Temperature stress will be characterized, models to explain the instability effects will be developed, the impact of processing, material composition and deposition techniques, annealing conditions etc. will be investigated, and ways to improve these BTI effects will be proposed. This work should ultimately lead to optimized gate stacks with higher BTI robustness 224 pp. Englisch.
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Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Aoulaiche MarcMarc Aoulaiche received the M.S. degree from the University of Provence (Aix-Marseille I), France, in 2004 and the PhD degree in microelectronics from the Interuniversity Microelectronics Ce…nter (IMEC), and Katholiek.
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Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -New MOSFET architectures are presently being developed in which dielectrics with high permittivity are introduced to replace SiO2-based dielectrics, which are at the end of the scaling roadmap, and where also metal gates are used to repla…ce poly-Si gate to avoid poly-depletion effects. Key in the success of this development is the electrical behavior of such high k/metal gate devices, and more specifically the Bias-Temperature- Instabilities, which are well-known reliability problems in MOS gate stacks. In this thesis, these Bias-Temperature effects will be investigated: the electrical behavior of the devices under Bias- Temperature stress will be characterized, models to explain the instability effects will be developed, the impact of processing, material composition and deposition techniques, annealing conditions etc. will be investigated, and ways to improve these BTI effects will be proposed. This work should ultimately lead to optimized gate stacks with higher BTI robustnessVDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 224 pp. Englisch.
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Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - New MOSFET architectures are presently being developed in which dielectrics with high permittivity are introduced to replace SiO2-based dielectrics, which are at the end of the scaling roadmap, and where also metal gates are used to replac…e poly-Si gate to avoid poly-depletion effects. Key in the success of this development is the electrical behavior of such high k/metal gate devices, and more specifically the Bias-Temperature- Instabilities, which are well-known reliability problems in MOS gate stacks. In this thesis, these Bias-Temperature effects will be investigated: the electrical behavior of the devices under Bias- Temperature stress will be characterized, models to explain the instability effects will be developed, the impact of processing, material composition and deposition techniques, annealing conditions etc. will be investigated, and ways to improve these BTI effects will be proposed. This work should ultimately lead to optimized gate stacks with higher BTI robustness.
