9786200218933 - A Phase Locked Loop Based Integer N Frequency Synthesizer von Patra, Jyoti P.; Pati, Umesh C. (8 Ergebnisse)

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Taschenbuch. Zustand: Neu. A Phase Locked Loop Based Integer N Frequency Synthesizer | Jyoti P. Patra (u. a.) | Taschenbuch | 76 S. | Englisch | 2019 | LAP LAMBERT Academic Publishing | EAN 9786200218933 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The present work describes about a phase locked loop (PLL) based integer n frequency synthesizer for unlicensed national information infrastructure (UNII) lower band. It covers a frequency range of 5.15 - 5.25 GHz which is used by IEEE 802.11a. For simplification of design, the channel spacing of the frequency synthesizer is taken to be 5 MHz. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a second order loop filter (LP), a voltage controlled oscillator (VCO) and a programmable divider block (PD). The dual modulus prescaler based programmable divider is used for the frequency synthesizer purpose because it is the most popular technique due to its versatility and facility of implementation. All the frequency synthesizer components are modeled using SIMULINK environment. The frequency synthesizer performance is simulated in terms of Root locus, step response and Bode plot methods using MATLAB in order to check the correct transfer function and stability. Simulation results of the integer frequency synthesizer confirm the validation of the model. 76 pp. Englisch.

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Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Patra Jyoti P.Jyoti Prasanna Patra received his Ph.D and M.tech degree from NIT Rourkela in the 2018 and 2012 respectively. He has completed his B.Tech from C.V. Raman College of Engineering, Bhubaneswar. Currently, he is working a.

Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The present work describes about a phase locked loop (PLL) based integer n frequency synthesizer for unlicensed national information infrastructure (UNII) lower band. It covers a frequency range of 5.15 - 5.25 GHz which is used by IEEE 802.11a. For simplification of design, the channel spacing of the frequency synthesizer is taken to be 5 MHz. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a second order loop filter (LP), a voltage controlled oscillator (VCO) and a programmable divider block (PD). The dual modulus prescaler based programmable divider is used for the frequency synthesizer purpose because it is the most popular technique due to its versatility and facility of implementation. All the frequency synthesizer components are modeled using SIMULINK environment. The frequency synthesizer performance is simulated in terms of Root locus, step response and Bode plot methods using MATLAB in order to check the correct transfer function and stability. Simulation results of the integer frequency synthesizer confirm the validation of the model.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 76 pp. Englisch.

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The present work describes about a phase locked loop (PLL) based integer n frequency synthesizer for unlicensed national information infrastructure (UNII) lower band. It covers a frequency range of 5.15 - 5.25 GHz which is used by IEEE 802.11a. For simplification of design, the channel spacing of the frequency synthesizer is taken to be 5 MHz. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a second order loop filter (LP), a voltage controlled oscillator (VCO) and a programmable divider block (PD). The dual modulus prescaler based programmable divider is used for the frequency synthesizer purpose because it is the most popular technique due to its versatility and facility of implementation. All the frequency synthesizer components are modeled using SIMULINK environment. The frequency synthesizer performance is simulated in terms of Root locus, step response and Bode plot methods using MATLAB in order to check the correct transfer function and stability. Simulation results of the integer frequency synthesizer confirm the validation of the model.