Asic design opensparc processor von farag mohamed (8 Ergebnisse)

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Taschenbuch. Zustand: Neu. ASIC Design of the Opensparc T1 Processor Core | Mohamed Mahmoud Mohamed Farag | Taschenbuch | 192 S. | Englisch | 2013 | Scholars' Press | EAN 9783639512298 | Verantwortliche Person für die EU: Scholars Press, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu. …

Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -OpenSPARC T1 is the first open-source, multi-threaded and multi-cored processor developed by SUN micro-systems. The objective of this book is to carry out an ASIC design of the core of this processor using the 130nm CMOS technology. Starting from the open-source RTL description of the OpenSPARC T1 processor core, several modifications like memory mapping, reducing the processor threads and suppressing the test pins were made in order to reduce the processor size to fir it into a 4 x 4 mm2 die area as required by the technology supplier. The correct functionality of the modified RTL description of this processor was verified against over 500 test scripts given by SUN Inc. Next, to convert the design from the RTL form to its gate level equivalent the design was synthesized. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance. 192 pp. Englisch.…

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - OpenSPARC T1 is the first open-source, multi-threaded and multi-cored processor developed by SUN micro-systems. The objective of this book is to carry out an ASIC design of the core of this processor using the 130nm CMOS technology. Starting from the open-source RTL description of the OpenSPARC T1 processor core, several modifications like memory mapping, reducing the processor threads and suppressing the test pins were made in order to reduce the processor size to fir it into a 4 x 4 mm2 die area as required by the technology supplier. The correct functionality of the modified RTL description of this processor was verified against over 500 test scripts given by SUN Inc. Next, to convert the design from the RTL form to its gate level equivalent the design was synthesized. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance.…

Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Farag Mohamed Mahmoud MohamedElectronics And Communication Engineer, graduated from Cairo University 2007. Awarded Master Of Science on this work in 2013.OpenSPARC T1 is the first open-source, multi-threaded and multi-cored proce.…

Zustand: New. Print on Demand.

Zustand: New. PRINT ON DEMAND.

Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -OpenSPARC T1 is the first open-source, multi-threaded and multi-cored processor developed by SUN micro-systems. The objective of this book is to carry out an ASIC design of the core of this processor using the 130nm CMOS technology. Starting from the open-source RTL description of the OpenSPARC T1 processor core, several modifications like memory mapping, reducing the processor threads and suppressing the test pins were made in order to reduce the processor size to fir it into a 4 x 4 mm2 die area as required by the technology supplier. The correct functionality of the modified RTL description of this processor was verified against over 500 test scripts given by SUN Inc. Next, to convert the design from the RTL form to its gate level equivalent the design was synthesized. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 192 pp. Englisch.…