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In den WarenkorbHardcover. Zustand: Very Good. No Jacket. Former library book; May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 0.88.
Verlag: Springer International Publishing, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Sprache: Englisch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
EUR 106,99
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In den WarenkorbBuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Verlag: Springer International Publishing, Springer Nature Switzerland Jul 2017, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Sprache: Englisch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
EUR 106,99
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In den WarenkorbBuch. Zustand: Neu. Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 156 pp. Englisch.
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In den WarenkorbZustand: New. In.
Verlag: Springer International Publishing, Springer International Publishing, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Sprache: Englisch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
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In den WarenkorbTaschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Verlag: Springer International Publishing, Springer International Publishing Mai 2018, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Sprache: Englisch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
EUR 117,69
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In den WarenkorbTaschenbuch. Zustand: Neu. Neuware Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 156 pp. Englisch.
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes Königreich
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In den WarenkorbZustand: New. In.
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In den WarenkorbZustand: New.
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In den WarenkorbZustand: New.
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In den WarenkorbHardcover. Zustand: Brand New. 146 pages. 9.25x6.25x0.50 inches. In Stock.
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In den WarenkorbZustand: New.
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In den WarenkorbZustand: New. pp. 146.
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In den WarenkorbPaperback. Zustand: Brand New. reprint edition. 146 pages. 9.25x6.10x0.36 inches. In Stock.
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In den WarenkorbZustand: New.
Verlag: Springer International Publishing, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Sprache: Englisch
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In den WarenkorbGebunden. Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applicationsModels the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurementsDescribes various memory op.
Verlag: Springer International Publishing, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Sprache: Englisch
Anbieter: moluna, Greven, Deutschland
EUR 98,54
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In den WarenkorbZustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applicationsModels the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurementsDescribes various memory op.
Verlag: Springer International Publishing Jul 2017, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Sprache: Englisch
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
EUR 106,99
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In den WarenkorbBuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. 156 pp. Englisch.
Verlag: Springer International Publishing Mai 2018, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Sprache: Englisch
Anbieter: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
EUR 117,69
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In den WarenkorbTaschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. 156 pp. Englisch.
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In den WarenkorbZustand: New. PRINT ON DEMAND.
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In den WarenkorbZustand: New. Print on Demand.
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In den WarenkorbZustand: New. Print on Demand pp. 146.
Anbieter: Biblios, Frankfurt am main, HESSE, Deutschland
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In den WarenkorbZustand: New. PRINT ON DEMAND pp. 146.