The impact of vector and parallel architectures on the Gaussian elimination algorithm / Yves Robert

Robert, Yves (1958-)

ISBN 10: 0719033659 / ISBN 13: 9780719033650

Verlag: Manchester New York : Manchester University Press ; Halsted, 1990

Beschreibung

Fine copy in the original colour-printed boards. Remains particularly well-preserved overall; tight, bright, clean and strong. Physical description; x, 194 pp., illustrations, 24 cm. Notes; Includes bibliography (pp. 183-191) and index. Subjects; Computer architecture.Vector processing (Computer science). Parallel processing (Electronic computers). Algorithms. Gaussian processes. 1 Kg.

Bestandsnummer des Verkäufers 386038

Bibliografische Details

• Titel: The impact of vector and parallel architectures on the Gaussian elimination algorithm / Yves Robert
• Verlag: Manchester New York : Manchester University Press ; Halsted
• Erscheinungsjahr: 1990
• Sprache: Englisch
• ISBN-10: 0719033659
• ISBN-13: 9780719033650
• Einband: Hardcover
• Auflage: 1st edition.
• Gewicht: 1 Kilogramm

Über diesen Titel

Inhaltsangabe

The thesis of this book is that the design of efficient parallel algorithms is dependent on a knowledge of the underlying parallel architecture. The first part of the book is implementation oriented, whereas the second part is devoted to design tools and methodologies. The first section of the book contains some background information on Gaussian elimination and parallel processing terminology and an introduction to pipeline, vector and parallel architectures. The next three chapters of the book are implementation oriented, describing the restructuring techniques needed for shared memory vector multiprocessors, distributed memory systems and systolic arrays. The book describes the recasting of the Gaussian elimination algorithm in terms of vector-vector, vector-matrix and matrix-matrix kernels, discusses hypercube computing and gives real-life examples of implementations on message-passing distributed memory systems. The last three chapters are more theoretical. Subjects covered include task graph scheduling, complexity results and speedup evaluation in a distributed memory environment and automatic synthesis methods for systolic arrays.