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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing, Band 22) - Hardcover
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Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.
Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
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Zustand: New. Focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. This text surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths. Series: Frontiers in Electronic Testing. Num Pages: 189 pages, biography. BIC Classification: TJFD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 297 x 210 x 12. Weight in Grams: 990. . 2003. Hardback. . . . . Bestandsnummer des Verkäufers V9781402072352
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Buch. Zustand: Neu. Power-Constrained Testing of VLSI Circuits | A Guide to the IEEE 1149.4 Test Standard | Bashir M. Al-Hashimi (u. a.) | Buch | Frontiers in Electronic Testing | xi | Englisch | 2003 | Springer US | EAN 9781402072352 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. Bestandsnummer des Verkäufers 102573476
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Power-Constrained Testing of VLSI Circuits
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Buch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 192 pp. Englisch. Bestandsnummer des Verkäufers 9781402072352
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Zustand: New. Focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. This text surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths. Series: Frontiers in Electronic Testing. Num Pages: 189 pages, biography. BIC Classification: TJFD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 297 x 210 x 12. Weight in Grams: 990. . 2003. Hardback. . . . . Books ship from the US and Ireland. Bestandsnummer des Verkäufers V9781402072352
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Buch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented. 192 pp. Englisch. Bestandsnummer des Verkäufers 9781402072352
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