Energy Efficient and Fault-tolerant Computing : A comprehensive manual on hardware and micro-architecture techniques for fault-tolerance, low power and high performance

Jayaram Natarajan

ISBN 10: 6138916204 / ISBN 13: 9786138916208

Verlag: Scholars' Press, 2019

Beschreibung

nach der Bestellung gedruckt Neuware - Printed after ordering - One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.

Bestandsnummer des Verkäufers 9786138916208

Bibliografische Details

• Titel: Energy Efficient and Fault-tolerant Computing : A comprehensive manual on hardware and micro-architecture techniques for fault-tolerance, low power and high performance
• Verlag: Scholars' Press
• Veröffentlichungsdatum: 2019
• Sprache: Englisch
• ISBN-10: 6138916204
• ISBN-13: 9786138916208
• Bindung: Taschenbuch
• Zustand: Neu

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Inhaltsangabe

One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.