Formal Semantics and Proof Techniques for Optimizing VHDL Models

Umamageswaran Kothanda Wilsey Philip A. Pandey Sheetanshu L.

ISBN 10: 0792383753 / ISBN 13: 9780792383758

Verlag: Springer, 1998

Beschreibung

pp. 184 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.

Bestandsnummer des Verkäufers 7547249

Bibliografische Details

• Titel: Formal Semantics and Proof Techniques for Optimizing VHDL Models
• Verlag: Springer
• Erscheinungsjahr: 1998
• Sprache: Englisch
• ISBN-10: 0792383753
• ISBN-13: 9780792383758
• Einband: Hardcover
• Zustand: New

Über diesen Titel

Inhaltsangabe

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.