3D Networks-on-Chip Architecture Optimization for Low Power Design

Michael Opoku Agyeman

ISBN 10: 3659758132 / ISBN 13: 9783659758133

Verlag: LAP LAMBERT Academic Publishing, 2015

Beschreibung

nach der Bestellung gedruckt Neuware - Printed after ordering - Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.

Bestandsnummer des Verkäufers 9783659758133

Bibliografische Details

• Titel: 3D Networks-on-Chip Architecture Optimization for Low Power Design
• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsjahr: 2015
• Sprache: Englisch
• ISBN-10: 3659758132
• ISBN-13: 9783659758133
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 220B x 150 H x 11 T Millimeter Breite: 220 mm, Höhe: 150 mm, Tiefe: 11 mm
• Gewicht: 286 Gramm

Über diesen Titel

Inhaltsangabe

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.