Performance Evaluation of 3D SRAM Architecture using Coaxial TSV

R. Arun Prasath

ISBN 10: 3659746495 / ISBN 13: 9783659746499

Verlag: LAP Lambert Academic Publishing Jul 2015, 2015

Beschreibung

Neuware -3D stacking of logic and memory devices is essential to keep the Moore¿s law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multiple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.Books on Demand GmbH, Überseering 33, 22297 Hamburg 68 pp. Englisch.

Bestandsnummer des Verkäufers 9783659746499

Bibliografische Details

• Titel: Performance Evaluation of 3D SRAM Architecture using Coaxial TSV
• Verlag: LAP Lambert Academic Publishing Jul 2015
• Erscheinungsjahr: 2015
• Sprache: Englisch
• ISBN-10: 3659746495
• ISBN-13: 9783659746499
• Einband: Taschenbuch
• Zustand: Neu
• Abmessungen: 220B x 150 H x 5 T Millimeter Breite: 220 mm, Höhe: 150 mm, Tiefe: 5 mm
• Gewicht: 119 Gramm

Über diesen Titel

Inhaltsangabe

3D stacking of logic and memory devices is essential to keep the Moore's law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multiple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.