Verilog and SystemVerilog Gotchas
Don Mills
Verkauft von BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
AbeBooks-Verkäufer seit 11. Januar 2012
Neu - Hardcover
Zustand: Neu
Anzahl: 2 verfügbar
In den Warenkorb legenVerkauft von BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Deutschland
AbeBooks-Verkäufer seit 11. Januar 2012
Zustand: Neu
Anzahl: 2 verfügbar
In den Warenkorb legenThis item is printed on demand - it takes 3-4 days longer - Neuware -In programming, 'Gotcha' is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages. 240 pp. Englisch.
Bestandsnummer des Verkäufers 9780387717142
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
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