Jelte peter vink (6 Ergebnisse)

Taschenbuch. Zustand: Neu. Performance Analysis of SoC Architectures based on Network Calculi | Mathematical Modeling, Analysis and Case studies | Jelte Peter Vink | Taschenbuch | 164 S. | Englisch | 2010 | LAP LAMBERT Academic Publishing | EAN 9783843351102 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.…

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Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This thesis describes a method for static performance analysis for obtaining upper bounds on delay and buffering requirements in a SoC architecture. The method is based on network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. The power of the performance analysis method is demonstrated by analyzing several schedule and interconnect variants for a multi-channel DVB-T set-top box case study. The influence of the frequency of the memory system and the pipeline degree of the traffic streams is shown. Furthermore, the influence of the packet size on the buffering requirements is analyzed. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options. 164 pp. Englisch.…

Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Vink Jelte PeterJelte Peter Vink received his B.Sc. (Cum Laude) degree in Computer Science and Engineering and M.Sc. (Cum Laude) degree in Embedded Systems from Eindhoven University of Technology, the Netherlands, in 2005 and 2007 re.…

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This thesis describes a method for static performance analysis for obtaining upper bounds on delay and buffering requirements in a SoC architecture. The method is based on network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. The power of the performance analysis method is demonstrated by analyzing several schedule and interconnect variants for a multi-channel DVB-T set-top box case study. The influence of the frequency of the memory system and the pipeline degree of the traffic streams is shown. Furthermore, the influence of the packet size on the buffering requirements is analyzed. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.…

Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This thesis describes a method for static performance analysis for obtaining upper bounds on delay and buffering requirements in a SoC architecture. The method is based on network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. The power of the performance analysis method is demonstrated by analyzing several schedule and interconnect variants for a multi-channel DVB-T set-top box case study. The influence of the frequency of the memory system and the pipeline degree of the traffic streams is shown. Furthermore, the influence of the packet size on the buffering requirements is analyzed. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 164 pp. Englisch.…