ISBN: 9783659899485 - comparative study on reduction of sub-threshold leakage current (6 Ergebnisse)

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Taschenbuch. Zustand: Neu. Comparative Study on Reduction of Sub-Threshold Leakage Current | Kalagadda Bikshalu (u. a.) | Taschenbuch | 100 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659899485 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractor circuits using microwind tool. 100 pp. Englisch.…

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractor circuits using microwind tool. …

Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Bikshalu KalagaddaDr. Kalagadda Bikshalu received Ph.D from JNTUH, Hyderabad and M.Tech in Digital Electronics & Communication Systems and B.Tech in ECE from JNTU, Hyderabad. Presently he is working as Assistant professor in Dept. …

Taschenbuch. Zustand: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractor circuits using microwind tool.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 100 pp. Englisch. …