Comparative Study on Reduction of Sub-Threshold Leakage Current - Softcover

Bikshalu, Kalagadda; Madhavi Latha, Pedada

Softcover

ISBN 10: 3659899488 ISBN 13: 9783659899485

Verlag: LAP LAMBERT Academic Publishing, 2016

Inhaltsangabe

In order to deal with the active power utilization of high-performance digital designs, dynamic leakage control techniques are required to contribute considerable leakage power savings. As technology scales, sub threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. The main objective of this project is to reduce the sub-threshold leakage in a CMOS device by making use of sleep transistors and PMOS logic. A low resistance path is generated by using sleep transistors as keepers to drop down the sub-threshold leakage. This is achieved further by using PMOS logic between the pull-up network (PUN) and pull down network (PDN). A fast and efficient leakage reduction technique is put forward which mitigates the power dissipation in addition to the reduction of leakage current. The main objective of the work is to analyze power and delay at 130nm, 90nm, and 45nm technologies for a CMOS half and full adder as well as subtractor circuits using microwind tool.

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Über die Autorin bzw. den Autor

Dr. Kalagadda Bikshalu received Ph.D from JNTUH, Hyderabad and M.Tech in Digital Electronics & Communication Systems and B.Tech in ECE from JNTU, Hyderabad. Presently he is working as Assistant professor in Dept. of ECE, KUCE&T, Kakatiya University, India .His interests are High K dielectrics, Signal and Image processing and Low power VLSI

Details zur Ausgabe

• Verlag: LAP LAMBERT Academic Publishing
• Erscheinungsdatum: 2016
• Sprache: Englisch
• ISBN 10: 3659899488
• ISBN 13: 9783659899485
• Einband: Taschenbuch
• Anzahl der Seiten: 100
• Kontakt zum Hersteller: Nicht verfügbar
• Verantwortliche Person: Noor Publishing; customerservice@vdm-vsg.de; ; Brivibas gatve 197; Riga; 1039; Lettland