low power flash adc von subba reddy (5 Ergebnisse)

Taschenbuch. Zustand: Neu. Neuware -In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.Books on Demand GmbH, Überseering 33, 22297 Hamburg 80 pp. Englisch.

Taschenbuch. Zustand: Neu. Low Power Flash ADC | VLSI Technology | Murra Subba Reddy | Taschenbuch | 80 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783845440842 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Taschenbuch. Zustand: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC. 80 pp. Englisch.

Zustand: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Subba Reddy MurraIt describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.In this project, a new design for a low power CMOS flash Analog-to-Digital Conve.

Taschenbuch. Zustand: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.