VLSI Design and Test (Paperback)
Brajesh Kumar Kaushik
Verkauft von Grand Eagle Retail, Bensenville, IL, USA
AbeBooks-Verkäufer seit 12. Oktober 2005
Neu - Softcover
Zustand: Neu
Anzahl: 1 verfügbar
In den Warenkorb legenVerkauft von Grand Eagle Retail, Bensenville, IL, USA
AbeBooks-Verkäufer seit 12. Oktober 2005
Zustand: Neu
Anzahl: 1 verfügbar
In den Warenkorb legenPaperback. This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification. This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Bestandsnummer des Verkäufers 9789811074691
This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017.
The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.
This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017.
The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.
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