Power-Constrained Testing of VLSI Circuits : A Guide to the IEEE 1149.4 Test Standard

Bashir M. Al-Hashimi

ISBN 10: 1441953159 / ISBN 13: 9781441953155

Verlag: Springer US, 2010

Beschreibung

Druck auf Anfrage Neuware - Printed after ordering - Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Bestandsnummer des Verkäufers 9781441953155

Bibliografische Details

• Titel: Power-Constrained Testing of VLSI Circuits : A Guide to the IEEE 1149.4 Test Standard
• Verlag: Springer US
• Erscheinungsjahr: 2010
• Sprache: Englisch
• ISBN-10: 1441953159
• ISBN-13: 9781441953155
• Einband: Taschenbuch
• Zustand: Neu

Über diesen Titel

Inhaltsangabe

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Reseña del editor

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.